1. Field of the Invention
This present invention is generally relates to a method for forming gate dielectric layer in NROM (nitride read only memory) by using zirconium oxide layer to replace conventional silicon dioxide layer, and more particularly to a method for increasing gate controllability and good on and off characteristics.
2. Description of the Prior Art
Referring to FIG. 1, a typical prior art NROM cell is illustrated. This cell includes a substrate 100, an ONO (oxide-nitride-oxide) structure having a silicon nitride layer 122 sandwiched between two silicon oxide layers 120 and 124 formed thereon, and a polysilicon layer 150 formed on top of the ONO layer by using LPCVD (Low Pressure Chemical Vapor Deposition) method. Then, an etching step is performed to etch the polysilicon layer 150 and the ONO structure to form gate electrode and spacers 126 and 128 are then formed on the sidewall of gate electrode. Next, a source 101 and a drain 102 is implanted in the substrate 100.
For erasable programmable read only memory (EPROM), a cell includes a gate structure and a drain 102. A silicon oxide layer 120, which is the bottom layer of gate electrode, is thin enough to permit Fowler Nordheim tunneling (FN tunneling) occurred. Memory cell is therefore erased or programmed by FN tunneling through the bottom silicon oxide layer 120 which can be appeared as tunneling oxide layer. When in writing mode, gate electrode is grounded while the drain 102 is connected a high voltage. When in erasing mode, gate electrode is connected to a high voltage, while the drain 102 is grounded.
According to the hot electron injection phenomenon (HEI), some hot electrons penetrate through the bottom silicon oxide layer 120, especially when silicon oxide layer 120 is thin enough, and electrons are therefore collected in silicon nitride layer 122. As known in the art, the received charge retained in silicon nitride layer 122 is concentrated in the region adjacent to drain 102.
The conventional method for forming the tunneling oxide layer 120 is to form a silicon oxide layer on the substrate by thermal oxidation. However, the dielectric constant value of silicon dioxide is between about 3.8 to 3.9 and thermal oxidation is a high temperature process. Moreover, the gate dielectric layer has low coupling ratio and if we introduce high voltage to gate electrode/drain to erase/program the cell more than 100 times, tunneling oxide layer 120 is easily breakdown, leakage current is increased, and reliability of tunneling oxide layer 120 is decreased.
In accordance with this present invention, a method for forming a gate dielectric layer in NROM is provided, wherein a zirconium oxide layer replaces for conventional tunneling oxide layer.
It is a first object of this invention to deposit a zirconium oxide layer on the substrate by sputtering deposition method having lower process temperature than conventional thermal oxidation such that thermal budget can be reduced.
It is another object of this present invention that high coupling ratio gate dielectric layer formed on the substrate.
It is a further object of this present invention that high dielectric constant zirconium oxide layer formed on the substrate can reduce control voltage and increase current drivability, exhibit low subthreshold swing and well on/off characteristics.
It is still another object of this present invention that high coupling ratio of gate dielectric layer can be improved, and defect density of memory cell is reduced, and reliability of flash memory device can be improved.
In accordance to the above objects, in one embodiment for this present invention for the most part is to form a gate dielectric layer in NROM. The gate structure is constructed by a substrate and a zirconium oxide layer is formed on the substrate and a silicon nitride layer is sandwiched between the zirconium oxide layer and a silicon oxide layer. Then, a polysilicon layer is formed on silicon oxide layer and a defined photoresist layer is formed on the polysilicon layer. Further, the polysilicon layer, silicon oxide layer, silicon nitride layer and zirconium oxide layer are subsequently etched to form gate electrode. Next, a source and a drain are formed inside the substrate by using conventional ion implantation method.